Verilog workflow

This project is mostly to test out an alternative digital design workflow than what is taught at universities.

The design itself is quite simple. It is a Wishbone-UART interface. Over a wishbone bus, a master can ask to read or write a byte. When writing, the byte is transmitted over serial UART. When reading, the module tries to read a byte from a buffer that stores bytes that were received over UART.

The main focus lies on synthesis and (formal) verification. These are done with open-source tools. The power of open-source also allows me to experiment with CI (Continuous Integration).